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ps3422-0600 2365 ne hopkins court pullman, wa 99163-5601 tel: 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com www.aha.com advanced hardware architectures product specification aha3422 starlite tm 16 mbytes/sec lossless decompressor ic
advanced hardware architectures, inc. ps3422-0600 i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 conventions, notations and definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.0 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 data ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 dma mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 pad word handling in burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 dma request signals and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.1 fifo threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.2 request during an end-of-record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4.3 request status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 odd byte handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.1 input, pad bytes and error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.2 output and pad bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 video interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7.1 video output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.9 decompression engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.10 prearming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.12 duplex printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.13 blank bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.14 low power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.15 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.0 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 system configuration 0, address 0x00 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 system configuration 1, address 0x01 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 input fifo thresholds, address 0x02 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 output fifo thresholds, address 0x03 - read/write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5 decompression ports status, address 0x05 - read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 port control, address 0x06 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 interrupt status/control 0, address 0x07 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 interrupt mask 0, address 0x09 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 version, address 0x0a - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10 decompression record length, address 0x0c, 0x0d, 0x0e, 0x0f - read/write. . . . . . . . . . . . . . . . . . . . 18 4.11 decompression control, address 0x18 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 decompression reserved, address 0x1a, 0x3a - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 4.13 decompression line length, address 0x1c, 0x1d - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 4.14 interrupt status/control 1, address 0x27 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.15 interrupt mask 1, address 0x29 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.16 decompression record count, address 0x2c, 0x2d - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.17 pattern, address 0x35 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.18 decompression control prearm, address 0x38 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.19 control, address 0x3f - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
advanced hardware architectures, inc. ii ps3422-0600 5.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 video interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.0 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.0 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 7.1 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 absolute maximum stress ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.0 ac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 9.0 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.1 available parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.0 related technical publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 appendix a: additional timing diagrams for dma mode transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 appendix b: sequential register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
advanced hardware architectures, inc. ps3422-0600 iii figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2: microprocessor port write (procmode[1:0]=?01?). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3: microprocessor port read (procmode[1:0]=?01?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4: microprocessor port write (procmode[1:0]=?11?). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 5: microprocessor port read (procmode[1:0]=?11?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6: dma mode timing for single word writes, strobe condition of dsc=100 . . . . . . . . . . . . . . . . . . . . . . . 6 figure 7: dma mode timing for single word reads, strobe condition of dsc=100 . . . . . . . . . . . . . . . . . . . . . . . 6 figure 8: dma mode timing for four word burst write, one wait state, strobe condition of dsc=100. . . . . . . . 6 figure 9: dma mode timing for four word burst read, one wait state, strobe condition of dsc=100 . . . . . . . 7 figure 10: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=100 . . . . . . . 7 figure 11: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=100 . . . . . . . 7 figure 12: fifo threshold example (ift=4, dsc=2, 1 word already in fifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 13: request vs. end-of-record, strobe condition of dsc=010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 14: timing diagram, video output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 15: pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16: data interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 17: request deasserts at eor, strobe condition of dsc=0-3, 6-15; erc=0 . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18: request deasserts at eor, strobe condition of dsc=0-3, 6-15; erc=1 . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19: request deasserts at eor, strobe condition of dsc=4 or 5; erc=0 . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 20: request deasserts at eor, strobe condition of dsc=4 or 5; erc=1 . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 21: output enable timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 22: video output port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 23: microprocessor interface timing (procmode[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 24: microprocessor interface timing (procmode[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 25: interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 26: clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 27: power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure a1: dma mode timing for single word writes, strobe condition of dsc=000 . . . . . . . . . . . . . . . . . . . . . . 37 figure a2: dma mode timing for single word reads, strobe condition of dsc=000 . . . . . . . . . . . . . . . . . . . . . . 37 figure a3: dma mode timing for four word burst write, one wait state, strobe condition of dsc=000. . . . . . . 37 figure a4: dma mode timing for four word burst read, one wait state, strobe condition of dsc=000 . . . . . . 38 figure a5: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=000 . . . . . . 38 figure a6: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=000 . . . . . . 38 figure a7: dma mode timing for single word writes, strobe condition of dsc=010 . . . . . . . . . . . . . . . . . . . . . . 39 figure a8: dma mode timing for single word reads, strobe condition of dsc=010 . . . . . . . . . . . . . . . . . . . . . . 39 figure a9: dma mode timing for four word burst write, one wait state, strobe condition of dsc=010. . . . . . . 39 figure a10: dma mode timing for four word burst read, one wait state, strobe condition of dsc=010 . . . . . . 40 figure a11: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=010 . . . . . . 40 figure a12: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=010 . . . . . . 40 figure a13: dma mode timing for single word writes, strobe condition of dsc=011 . . . . . . . . . . . . . . . . . . . . . . 41 figure a14: dma mode timing for single word reads, strobe condition of dsc=011 . . . . . . . . . . . . . . . . . . . . . . 41 figure a15: dma mode timing for four word burst write, one wait state, strobe condition of dsc=011. . . . . . . 41 figure a16: dma mode timing for four word burst read, one wait state, strobe condition of dsc=011 . . . . . . 42 figure a17: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=011 . . . . . . 42 figure a18: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=011 . . . . . . 42 figure a19: dma mode timing for single word writes, strobe condition of dsc=111 . . . . . . . . . . . . . . . . . . . . . . 43 figure a20: dma mode timing for single word reads, strobe condition of dsc=111 . . . . . . . . . . . . . . . . . . . . . . 43
advanced hardware architectures, inc. iv ps3422-0600 tables table 1: data bus and fifo sizes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2: connection to host microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 3: microprocessor port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 4: internal strobe conditions for dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 5: internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6: data port timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7: request vs. eor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8: output enable timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9: video output port timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10: microprocessor interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11: interrupt timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12: clock timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 13: power on reset timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ps3422-0600 page 1 of 44 advanced hardware architectures, inc. 1.0 introduction aha3422 is a lossless decompression coprocessor ic for hardcopy systems on many standard platforms. the device is targeted for high throughput and high resolution hardcopy systems. multiple record counters, higher clock frequency, advanced banding and duplex printing features enhance this product from the first starlite ? introduction, aha3410. identical decompression algorithm and similar firmware considerations ease migration to this second generation device. blank band generation in real time and prearming registers between records enable advanced banding techniques. bands may be in raw uncompressed, compressed or blank format in the frame buffer. the device processes all three formats and outputs the raster data to the printer engine. appropriate registers are prearmed when switching from one type to the next. byte ordering allows full reversal of the image data for duplex printing support. a system may use multiple record counters and end-of-transfer interrupts to easily handle pages partitioned into smaller records or bands. this document contains functional description, system configurations, register descriptions, electrical characteristics and ordering information. it is intended for system designers considering a decompression coprocessor in their embedded applications. software simulation and an analysis of the algorithm for printer and copier images of various complexity are also available for evaluation. a comprehensive designer?s guide complements this document to assist with the system design. section 11.0 contains a list of related technical publications. 1.1 conventions, notations and definitions ? active low signals have an ? n ? appended to the end of the signal name. for example, csn and rdyn. ? a ? bar ? over a signal name indicates an inverse of the signal. for example, sd indicates an inverse of sd. this terminology is used only in logic equations. ?? signal assertion ? means the output signal is logically true. ? hex values are represented with a prefix of ? 0x ? , such as register ? 0x00 ? . binary values do not contain a prefix, for example, dsc=000. ? a range of signal names or register bits is denoted by a set of colons between the numbers. most significant bit is always shown first, followed by least significant bit. for example, vod[7:0] indicates signal names vod7 through vod0. ? a logical ? and ? function of two signals is expressed with an ? & ? between variables. ? mega bytes per second is referred to as mbytes/ sec or mb/sec. ? in referencing microprocessors, an x, xx or xxx is used as suffix to indicate more than one processor. for example, motorola 68xxx processor family includes various 68000 processors from motorola. ? reserved bits in registers are referred as ? res ? . ? reqn or ackn refer to either di, or do request or acknowledge signals, as applicable. ? nc in pinout description means ? no connect ? . 1.2 features performance: 16 mbytes/sec maximum sustained data throughput 132 mbytes/sec burst data rate over a 32-bit data bus 33 mbytes/sec synchronous 8-bit video out port maximum clock speeds up to 33 mhz average 15 to 1 compression ratio for 1200 dpi bitmap image data advanced banding support: blank bands, prearming flexibility: big endian or little endian; 32 or 16-bit bus width and data byte reordering for duplex printing support prearmable registers scan line length up to 2k bytes interfaces directly with various mips, motorola 68xxx and cold fire, intel i960 embedded processors pass-through mode passes raw data through the decompression engine counter checks errors in decompression system interface: single chip decompression solution ? no external sram required two 16 32-bit fifos with programmable threshold counters facilitate burst mode transfers others: low power modes software emulation program available 128 pin quad flat package test pin tristates outputs
page 2 of 44 ps3422-0600 advanced hardware architectures, inc. figure 1: functional block diagram 1.3 functional overview the coprocessor device has two external high speed synchronous data ports capable of transferring once every clock cycle. these are a 32-bit bidirectional data port and a video output data (vod) port. the 32-bit port is capable of transferring up to 4 bytes per clock. the vod is capable of up to one byte per clock. decompression data is accepted through the 32- bit data port, buffered in the decompression input fifo (di fifo) and decompressed. the output data is made available on the 32-bit data port via the decompression output fifo (do fifo) or the 8- bit video output port. the decompression engine runs on the 33 mhz clock and is capable of processing an uncompressed byte every other clock. the two fifos are organized as 16 32 each. for data transfers through the two ports, the ? effective ? fifo sizes differ according to their data bus widths. the table below shows the size of the data port and the ? effective ? fifo size for the various configurations supported by the device. table 1: data bus and fifo sizes supported table 2: connection to host microprocessors d[31:0] driven test clk rstn procmode[1:0] pd[7:0] pa[5:0] csn dir rdyn intrn voackn vod[7:0] voreqn voeorn voeotn (to printer) data port di fifo 16x32 clock decompressor microprocessor interface do fifo 16x32 vod port aha3422 starlitetm 8 8 8 32 32 32 6 8 doreqn direqn sd doackn diackn data port control operation data bus width port effective fifo size decompression data in/out 32 data port 16 x 32 decompression data in/out 16 data port 16 x 16 decompressed data out 8 video out 16 x 8 pin name i960cx i960kx idt3081 motorola mcfs102(coldfire) pa a lad latched address latched address csn cs cs system dependent decoded chip select dir w/r w/r wr r/w pd d lad a/d a/d[7:0] sd wa it ready system dependent system dependent rdyn no connect ready ack ta driven den system dependent system dependent system dependent clock pclk no connect sysclk bclock
ps3422-0600 page 3 of 44 advanced hardware architectures, inc. movement of data for decompression is performed using synchronous dma over the 32-bit data port. the video port also supports synchronous dma mode transfers. the dma strobe conditions are configurable for the 32-bit data port depending upon the system processor and the available dma controller. data transfer for decompression is synchronous over the two data ports functioning as dma masters. to initiate a transfer out of the video port, the device asserts voreqn, the external device responds with voackn and begins to transfer data over the vod bus on each succeeding rising edge of the clock until voreqn is deasserted. the 32-bit port relies on the fifo threshold settings to determine the transfer. the sections below describe the various configurations, programming and other special considerations in developing a decompression system using aha3422. 2.0 system configuration this section provides information on connecting the device to various microprocessors. data throughput is internally controlled by writing a control code to the control register. if this feature is not used, the system must control data throughput to remain within the specified limit of 16 mbytes/sec. the control code for this device is 0x0e. 2.1 microprocessor interface the device is capable of interfacing directly to various processors for embedded application. table 2 and table 3 show how to connect to various host microprocessors. all register accesses are performed on the 8-bit pd bus. the pd bus is the lowest byte of the 32-bit microprocessor bus. during reads of the internal registers, the upper 24 bits are not driven. system designers should terminate these lines with pullup resistors. the part provides four modes of operation for the microprocessor port. both active high and active low write enable signals are allowed as well as two modes for chip select. the mode of operation is set by the procmode[1:0] pins. the procmode[1] signal selects when csn must be active and also how long an access lasts. when procmode[1] is high, csn determines the length of the access. csn must be at least 5 clocks in length. on a read, valid data is driven onto pd[7:0] during the 5th clock. if csn is longer than 5 clocks, then valid data continues to be driven out onto pd[7:0]. when csn goes inactive (high), pd[7:0] goes tristate (asynchronously) and rdyn is driven high asynchronously. csn must be high for at least two clocks. rdyn is always driven (it is not tristated when procmode[1] is high). the mode is typical of processors such as the motorola 68xxx. when procmode[1] is low, accesses are fixed at 5 clocks, pd[7:0] is only driven during the fifth clock, and rdyn is driven high for the first 4 clocks and low during the fifth clock. rdyn is tristated at all other times. write data must be driven the clock after csn is sampled low. accesses may be back to back with no delays in between. this mode is typical of risc processors such as the i960. procmode[0] determines the polarity of the dir pin. if procmode[0] is high, then the dir pin is an active low write enable. if procmode[0] is low, then the dir pin is an active high write enable. figure 2 through figure 5 illustrate the detailed timing diagrams for the microprocessor interface. for additional notes on interfacing to various microprocessors, refer to aha application note (andc16), designer?s guide for starlite tm family products . aha applications engineering is available to support with other processors not in the designer ? s guide. table 3: microprocessor port configuration procmode[1:0] dir cycle length example processor 00 active high write fixed i960 01 active low write fixed 10 active high write variable 11 active low write variable 68xxx, mips r3000
page 4 of 44 ps3422-0600 advanced hardware architectures, inc. figure 2: microprocessor port write (procmode[1:0]=?01?) figure 3: microprocessor port read (procmode[1:0]=?01?) figure 4: microprocessor port write (procmode[1:0]=?11?) clock pa[5:0] csn dir pd[7:0] a0 rdyn a1 d0 d1 clock pa[5:0] csn dir pd[7:0] a0 rdyn a1 d0 a2 d1 clock pa[5:0] csn dir pd[7:0] a0 rdyn a1 d0
ps3422-0600 page 5 of 44 advanced hardware architectures, inc. figure 5: microprocessor port read (procmode[1:0]= ? 11 ? ) 3.0 functional description this section describes the various data ports, special handling, data formats and clocking structure. 3.1 data ports the device contains one data input port, di, and one data output port, do, on the same 32-bit data bus, d[31:0]. data transfers are controlled by external dma control. the logical conditions under which data is written to the input fifo or read from the output fifo are set by the dsc (data strobe condition) field of the system configuration 1 register. a strobe condition defines under what logical conditions the input fifo is written or the output fifo read. diackn, doackn, and sd pins combine to strobe data in a manner similar to dma controllers. the dma mode sub-section describes the various data strobe options. 3.2 dma mode on the rising edge of clock when the strobe condition is met, the port with the active acknowledge either strobes data into or out of the chip. no more than one port may assert acknowledge at any one time. table 4 shows the various conditions that may be programmed into register dsc. figure 6 through figure 11 illustrate the dma mode timings for single, four word and eight word burst transfers for dsc=100 selection. for other dsc settings, please refer to appendix a. note that the only difference between odd and even values of dsc is the polarity of sd. waveforms are only shown for polarities of sd corresponding to specific systems. table 4: internal strobe conditions for dma mode clock pa[5:0] csn dir pd[7:0] a0 rdyn a1 d0 dsc[2:0] logic equation system configuration 000 i960cx with internal dma controller. sd is connected to wa i t n . 001 no specific system 010 general purpose dma controller 011 i960kx with external, bus master type dma controller. sd is connected to rdyn. 100 no specific system 101 no specific system 110 no specific system 111 no specific system ackn () & ackn delayed () & sd () ackn () & ackn delayed () & sd () ackn () & sd () ackn () & sd () ackn delayed () & sd delayed () ackn delayed () & sd delayed () ackn () & ackn delayed () ackn () & ackn delayed () ckn delayed ackn delayed 1 clock = sd delayed sd delayed 1 clock =
page 6 of 44 ps3422-0600 advanced hardware architectures, inc. figure 6: dma mode timing for single word writes, strobe condition of dsc=100 figure 7: dma mode timing for single word reads, strobe condition of dsc=100 figure 8: dma mode timing for four word burst write, one wait state, strobe condition of dsc=100 clock ackn sd driven d d0 d1 clock ackn sd driven d d1 d0 clock ackn sd driven d d0 d2 d1 d3
ps3422-0600 page 7 of 44 advanced hardware architectures, inc. figure 9: dma mode timing for four word burst read, one wait state, strobe condition of dsc=100 figure 10: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=100 figure 11: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=100 clock ackn sd driven d d1 d0 d2 d3 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7
page 8 of 44 ps3422-0600 advanced hardware architectures, inc. 3.3 pad word handling in burst mode a method is available to delete pad words during decompression. pad words may be deleted by using the decompression pause on record boundaries bit (dpor), in the decompression control register. after the part is paused, the di fifo must be reset by asserting the dirst bit in the port control register. decompressor must also be reset by asserting ddr bit in decompression control register. 3.4 dma request signals and status the part requests data using request pins (direqn, doreqn). the requests are controlled by programmable fifo thresholds. both input and output fifos have programmable empty and full thresholds set in the input fifo threshold and output fifo threshold registers. by requesting only when a fifo can sustain a certain burst size, the bus is used more efficiently. operation of these request signals should not be confused with the request signals on the video port. direqn active indicates space available in the input fifo and doreqn active indicates data is available in the output fifo. these request signals being inactive do not prevent data transfers. the data transfers are controlled solely with the particular acknowledge signal being active. the input request, direqn, operates under the following prioritized rules, listed in order of highest to lowest: 1) if the fifo reset in the port control register is active, the request is inactive. 2) if a fifo overflow interrupt is active, the request is inactive. 3) if the fifo is at or below the empty threshold, the request remains active. 4) if the fifo is at or above the full threshold, the request stays inactive. the output request, doreqn, operates under the following prioritized rules, listed in order of highest to lowest: 1) if the fifo reset in the port control register is active, the request is inactive. 2) if the output fifo underflow interrupt is active, the request is inactive. 3) if an eor is present in the output fifo, the request goes active. 4) if the output fifo is at or above the full threshold, the request goes active. 5) if an eor is read (strobed) out of the fifo, the request goes inactive during the same clock as the strobe (if erc=0), otherwise it goes inactive on the next clock. 6) if the output fifo is at or below the empty threshold, the request goes inactive. 3.4.1 fifo threshold for maximum efficiency, the fifo threshold should be set in such a way that the decompressor seldom runs out of data from the di fifo or completely fills the output fifo. the fifo is 16 words deep. for example, in a system with fixed 8-word bursts, good values for the thresholds are: iet=3, ift=4, oft=d, oet=c setting the input full threshold to one higher than the input empty threshold simply guarantees that the request deasserts as soon as possible. the latency between a word being strobed in and the request changing due to a fifo threshold condition is 3 clocks. this should be kept in mind when programming threshold values. refer to section 4.0 of aha application note (andc16), designer ? s guide for starlite tm family products for a more thorough discussion of fifo thresholds. the following figure shows an example of an input fifo crossing its full threshold.
ps3422-0600 page 9 of 44 advanced hardware architectures, inc. figure 12: fifo threshold example (ift=4, dsc=2, 1 word already in fifo) note: direqn deasserted when threshold counter exceeded ift=4, but additional words are read as long as ackn is asserted. figure 13: request vs. end-of-record, strobe condition of dsc=010 3.4.2 request during an end-of-record the request deasserts at an eor in one of two ways. if erc bit in system configuration 1 is zero, the request deasserts asynchronously during the clock where the eor is strobed out of the fifo. this leads to a long output delay for reqn, but may be necessary in some systems. for dsc values of 4 or 5, the request deasserts the first clock after the acknowledge pulse for the eor. if erc is set to one, then the request deasserts synchronously the clock after the eor is strobed out. the minimum low time on the request in this case is one clock. the request delay varies between the different strobe conditions. see section 8.0 ac electrical specifications for further details. 3.4.3 request status bits an external microprocessor can also read the value of each request using the direq and doreq bits in the decompression port status register. please note the request status bits are active high while the pins are active low. 3.5 data format the width of the d bus is selected with the wide bit in system configuration 0 . if wide=1, then d is a 32-bit bus. if wide=0, d is a 16-bit bus. if the bus is configured to be 16-bits wide (wide=0), all data transfers occur on d[15:0] and the upper 16 bits of the bus, d[31:16], should be terminated with pullup resistors. if wide=0, the fifo is sixteen words deep. clock d ciackn cireqn threshold 1 2 3 45 6 7 8 1 23 4 5 6 78 9 counter eor-2 clock d ciackn reqn eor-1 eor (erc=0) eorn reqn (erc=1)
page 10 of 44 ps3422-0600 advanced hardware architectures, inc. since the compression algorithm is byte oriented, it is necessary for aha3422 to know the ordering of the bytes within the word. the decomp big bit in system configuration 0 selects between big endian and little endian byte ordering. little endian stores the first byte in the lower eight bits of a word (d[7:0]). big endian stores the first byte in the uppermost eight bits of a word (d[31:24] for wide=1, d[15:8] for wide=0). 3.6 odd byte handling all data transfers to or from the device are performed on the d bus on word boundaries. since no provision is made for single byte transfers, occasionally words will contain pad bytes. following is a description of when these pad bytes are necessary for each of the data interfaces. 3.6.1 input, pad bytes and error checking the device recognizes the end of a record by the appearance of a special end-of-record sequence in the data stream. once this is seen, the remaining bytes in the current word are treated as pad bytes and discarded. the word following the end of the record is the beginning of the next record. the decompression record length (drlen) register can be used to provide error checking. the expected length of the decompressed record is programmed into the drlen register. the decompressor then counts down from the value in drlen to zero. a derr interrupt is issued if an eor is not read out of the decompressor when the counter expires or if an eor occurs before the counter expires (i.e., when the record lengths do not match). if the derr interrupt is masked, use of the drlen register is optional. when operating in pass-through mode, there is no end-of-record codeword for the decompressor to see. in pass-through mode, the user must set the record length in the drlen register. 3.6.2 output and pad bytes when the decompressor detects an end-of- record codeword, it will add enough pad bytes of value 0x00 to complete the current word as defined by the wide bit in the system configuration 0 register. for example, if a record ends on a byte other than the last byte in a word, the final word contains 1, 2 or 3 pad bytes. this applies to the 32- bit data port only, not the vod port. the vod port never outputs pad bytes since it is 8-bits wide. 3.7 video interface 3.7.1 video output the video output port is enabled by the vdoe bit in the system configuration 1 register. the port uses voreqn to indicate that the byte on vod[7:0] is valid. an 8-bit word is read each clock when both voreqn and voackn are sampled low on a rising edge of clock. pad bytes at an end of record are discarded by the video output port and do not appear on vod[7:0]. when the byte on vod[7:0] is the last byte in a record, the voeorn signal goes low. unlike a dma transfer, there are no pad bytes after an end-of-record. voeotn operates similar to voeorn. it flags the end of an output transfer of one or more decompressed records. voeotn is asserted when the end-of-record is at the output of the do fifo and the decompression record count has decremented to zero. the port requests whenever a valid byte is present on the output. the values in oet and oft are all ignored. the decompression output fifo is 16 bytes deep in this mode. the video output port can output up to one byte per clock. the dma interface cannot access the decompression output fifo when vdoe is set. figure 14: timing diagram, video output clock voreqn voackn vod[7:0] 0 3 1 2 4 5 voeorn/ voeotn
ps3422-0600 page 11 of 44 advanced hardware architectures, inc. 3.8 algorithm aha3422 efficiently implements an algorithm optimized for bitonal images. for some comparison data refer to the aha application note (andc13), compression performance: starlite tm : encodeb2 on bitonal images . a software emulation of the algorithm is available for evaluation. 3.9 decompression engine the decompression engine is enabled with the dcomp bit in the decompression control register. when the engine is enabled, it takes data from the di fifo as it becomes available. this data is either decompressed by the engine or passed through unaltered. pass-through mode is selected with the dpass bit. dpass may only be changed when dcomp is set to zero and demp is set to one. the contents of the dictionary are preserved when dcomp is changed. however, when dpass is changed, the contents are lost. consequently, aha3422 cannot be changed from pass-through mode to decompression mode or vice versa without losing the contents of the dictionary. the decompressor can be instructed to halt at the end of a record or an end of multiple-record transfer. if the dpor bit is set, the decompressor stops taking data out of the di fifo immediately after the last byte of a record, and the dcomp bit is cleared. if dpot bit is set the decompressor halts at the end of the multiple-record transfer. the demp bit indicates the decompressor has emptied of all data. decom- pression is restarted by setting the dcomp bit. if dpor or dpot is set and data from a second record enters the fifo immediately after the first record, bytes from the second record will have entered the decompressor prior to decoding the eor. an impli- cation of this is that bytes from the second record will remain in the decompressor and prevent demp from setting after all of the data from the first record has left the decompressor. this differs from operation of the compression engine. in either mode, a deor interrupt is generated when the last byte of a decom- pressed record is read out of the chip, and deot when the last byte of a transfer is read out of the chip. the decompressor takes data from the decompression input fifo at a maximum rate of 16 mbytes/sec. aha3422 can maintain this data rate as long as the decompression input fifo is not empty or the decompression output fifo is not full. caveat: changing the mode for the decompressor between records or multiple-record transfers must be done with the data of the following record or transfer held off until the deor status bit is true for the current record and the decompression control registers have been reprogrammed. this reprogramming can occur automatically with prearming. 3.10 prearming prearming is the ability to write certain registers that apply to the next record while the device is processing the current record. these registers may be prearmed for record boundaries. prearming is automatic, meaning there is no way to disable it. if a prearmable register is written while the part is busy processing a record, at the end of the record the part takes its program from the register value last written. decompression control register has a corresponding prearm register. the lower 3 bytes of decompression length register are prearmable. if the most significant byte of this register is written to, the counter is immediately loaded with the current 4 byte value. if the most significant byte is not written to the counter, the counter gets reloaded at the end of the current record. 3.11 interrupts five conditions are reported in the interrupt status/control 0 and status/control 1 registers as individual bits. all interrupts are maskable by setting the corresponding bits in the interrupt mask register. a one in the interrupt mask register means the corresponding bit in the interrupt status/control register is masked and does not affect the interrupt pin (intrn). the intrn pin is active whenever any unmasked interrupt bit is set to a one. an end-of-record interrupt is posted when a word containing an end-of-record is strobed out of the decompression output fifo (deor). a deor interrupt is also reported if an end-of-record is read from the video output port. a decompression end of transfer interrupt will be posted if this is the last record of a transfer. end-of-transfer interrupt (deot) is posted when an eor occurs that causes the counter to decrement to zero. two fifo error conditions are also reported. overflowing the input fifo generates a diof interrupt. an overflow can only be cleared by resetting the fifo via the port control register. underflowing the output fifo (reading when it is not ready) generates a douf. the underflow interrupt is cleared by writing a one to douf. in the event of an underflow, the fifo must be reset.
page 12 of 44 ps3422-0600 advanced hardware architectures, inc. 3.12 duplex printing duplex printing is the ability to print on both sides of the page. aha3422 supports this with endian control. during decompression of this reversed page the big bit in this register must be programmed to the same value used when this page of data was compressed. use of this feature has virtually no effect on the decompression ratio when compared to decompressing in forward order. 3.13 blank bands setting dblank in the decompression control register causes the next record output from the decompressor to be comprised of a repeating 8- bit pattern defined by the pattern register. dblank automatically clears at the end of the next record. this command bit may be prearmed by writing to the decompression control prearm register. when programming the device to generate blank records the system must not send data to be decompressed until the device has reached the end of record for the blank record. 3.14 low power mode the device is a data-driven system. when no data transfers are taking place, only the clock and on-chip rams including the fifos require power. to reduce power consumption to its absolute minimum, the user can stop the clock when it is high. with the system clock stopped and at a high level, the current consumption is due to leakage. control and status registers are preserved in this mode. reinitialization of control registers are not necessary when switching from low power to normal operating mode. 3.15 test mode in order to facilitate board level testing, the device provides the ability to tristate all outputs. when the test0 pin is high, all outputs of the chip are tristated. when test0 is low, the chip returns to normal operation.
ps3422-0600 page 13 of 44 advanced hardware architectures, inc. 4.0 register descriptions the microprocessor configures, controls and monitors ic operation through the use of the registers defined in this section. the bits labeled ? res ? are reserved and must be set to zero when writing to registers unless otherwise noted. always program the control register (address 0x3f) with a value of 0x0e following power on and any hard reset. this should be done prior to accessing any other registers. a summary of registers is listed below. table 5: internal registers address r/w description function default after rstn prearm 0x00 r/w system configuration 0 big endian vs. little endian, 32-bit vs. 16-bit undefined no 0x01 r/w system configuration 1 data strobe condition, eor request control, vdo port enable 0x00 no 0x02 r/w input fifo thresholds input fifo empty threshold, full threshold undefined no 0x03 r/w output fifo thresholds output fifo empty threshold, full threshold undefined no 0x04 r reserved reserved undefined 0x05 r decompression ports status fifo status, request status, eor status undefined no 0x06 r/w port control 1 reset individual fifos 0x0f no 0x07 r/w interrupt status/control 0 eor, overflow, underflow 0x00 no 0x09 r/w interrupt mask 0 interrupt mask bits 0xff no 0x0a r version die version number 0x21 no 0x0c r/w decompression record length 0 bytes remaining, byte 0 0xff yes 0x0d r/w decompression record length 1 bytes remaining, byte 1 0xff yes 0x0e r/w decompression record length 2 bytes remaining, byte 2 0xff yes 0x0f r/w decompression record length 3 bytes remaining, byte 3 0xff no 0x10 r reserved reserved undefined 0x11 r reserved reserved undefined 0x12 r reserved reserved undefined 0x13 r reserved reserved undefined 0x14 r reserved reserved 0x04 0x15 r reserved reserved 0x00 0x16 r reserved reserved undefined 0x17 r reserved reserved undefined 0x18 r/w decompression control pause on record boundaries, enable decompression engine, decompression engine empty status, dictionary reset, enable pass-through mode, pause end-of-transfer, generate blank record, enable prearm 0x04 yes
page 14 of 44 ps3422-0600 advanced hardware architectures, inc. 0x1a r/w decompression reserved 1 reserved 0x00 no 0x1c r/w decompression line length 0 line length register lower 8bits undefined no 0x1d r/w decompression line length 1 line length register upper 3bits undefined no 0x20 r reserved reserved ff 0x21 r reserved reserved ff 0x27 r/w interrupt status/control 1 decompression eot interrupt 0x00 no 0x29 r/w interrupt mask 1 interrupt mask bit for deot 0xff no 0x2c r/w decompression record count 0 decompressor number of records in a transfer 0xff no 0x2d r/w decompression record count 1 decompressor number of records in a transfer 0xff no 0x30 r reserved reserved 0x00 0x31 r reserved reserved 0x00 0x32 r reserved reserved 0x00 0x33 r reserved reserved 0x00 0x34 r reserved reserved 0x00 0x35 r/w pattern 8-bit pattern for blank record generation undefined no 0x38 r/w decompression control prearm prearm register for decompression control 0x00 no 0x3a r/w decompression reserved 2 reserved 0x00 no 0x3f r/w control program to 0x0e 0x0f no address r/w description function default after rstn prearm
ps3422-0600 page 15 of 44 advanced hardware architectures, inc. 4.1 system configuration 0, address 0x00 - read/write after reset, its contents are undefined. it must be written before any input or output data movement may be performed. after changing this register, reset fifos via the port control register. big- selects between little or big endian byte order for the decompressor. see table. res - bits must always be written with zeros. wide - selects between 32 and 16-bit d buses. 4.2 system configuration 1, address 0x01 - read/write this register is cleared by reset. dsc[2:0] - data strobe condition. control the condition used to strobe data into and out of the data ports on the d bus. table 4 shows the programming for the strobe condition for various dma modes. res - bits must always be written with zeros. erc - eor request control. determines when doreqn deasserts at an end-of-record. if erc=0, then the request deasserts asynchronously during the clock when an eor is strobed out. if erc=1, then the request deasserts synchronously the clock after an eor is strobed out. see figure 17 through figure 20. vdoe - vdo port enable. when this bit is set, the data from the decompression output fifo goes to the vdo port. when the bit is clear, the decompressed data is read by dma on the d bus. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 res wide res big res comp big or decomp big wide description 0 0 little endian data order 16-bit words d[15:8] d[7:0] byte 1 byte 0 0 1 little endian data order 32-bit words d[31:24] d[23:16] d[15:8] d[7:0] byte 3 byte 2 byte 1 byte 0 1 0 big endian data order 16-bit words d[15:8] d[7:0] byte 0 byte 1 1 1 big endian data order 32-bit words d[31:24] d[23:16] d[15:8] d[7:0] byte 0 byte 1 byte 2 byte 3 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x01 res vdoe erc res dsc[2:0]
page 16 of 44 ps3422-0600 advanced hardware architectures, inc. 4.3 input fifo thresholds, address 0x02 - read/write after reset, its contents are undefined. it must be written before any input or output data movement may be performed. iet[3:0] - empty threshold for the input fifo. if the number of words in the input fifo (di) is less than or equal to this number, the request for that channel is asserted. ift[3:0] - full threshold for the input fifo. if the number of words in the input fifo (di) is greater than or equal to this number, the request for the channel is deasserted. 4.4 output fifo thresholds, address 0x03 - read/write after reset, its contents are undefined. it must be written before any input or output data movement may be performed. oet[3:0] - empty threshold for the output fifo. if the number of words in the output fifo (do) is less than or equal to this number, the request for the channel is deasserted (except in the case of an end-of-record). oft[3:0] - full threshold for the output fifo. if the number of words in the output fifo (do) is greater than or equal to this number, the request for that channel is asserted. 4.5 decompression ports status, address 0x05 - read only this is a read only register. writing to this register has no effect. after reset, its contents are undefined. dift - decompression input fifo full threshold. this signal is active when the di fifo is at or above the programmed fifo full threshold. after reset and the input fifo threshold register has been written, this bit contains a zero. direq - decompression input request signal state. reports the current state for the direqn pin. notice that this bit is active high while the pin is active low. therefore, the value of this bit is always the inverse of the value of the signal. after reset this bit contains a zero. doet - decompression output fifo empty threshold. this bit is active when the do fifo is at or below the programmed fifo empty threshold. after reset and the output fifo threshold register has been written, this bit contains a one. doreq - decompression output request signal state. reports the current state for the doreqn pin. notice that this bit is active high while the pin is active low. therefore, the value of this bit is always the inverse of the value of the signal. after reset this bit contains a zero. deor - decompression output end of record. this bit is active when the output fifo contains the end- of-record code. after reset this bit contains a zero. res - bits must always be written with zeros. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x02 ift[3:0] iet[3:0] address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x03 oft[3:0] oet[3:0] address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x05 doemp diemp res deor doreq doet direq dift
ps3422-0600 page 17 of 44 advanced hardware architectures, inc. diemp - decompression input empty. this bit is active when the di fifo is empty. after reset this bit contains a one. doemp - decompression output empty. this bit is active when the do fifo is empty. after reset this bit contains a one. 4.6 port control, address 0x06 - read/write this register is initialized to 0x0f after reset. dirst - decompression input reset. setting this bit to a one resets the di fifo and clears the state machines in the decompression input port. the reset condition remains active until the microprocessor writes a zero to this bit. dorst - decompression output reset. setting this bit to a one resets the do fifo and clears the state machines in the decompression output port. the reset condition remains active until the microprocessor writes a zero to this bit. res - bits must always be written with zeros. 4.7 interrupt status/control 0, address 0x07 - read/write this register is initialized to 0x00 after reset. deor - decompression end-of-record interrupt. this bit is set when the last byte of a record is strobed out of the decompression dma or video output port. the microprocessor must write a one to this bit to clear this interrupt. derr - decompression error. this bit is set if an eor leaves the decompressor before drlen has counted down to zero or if drlen counts to zero and the last byte is not an eor. derr is only active in decompression mode (dpass=0). the microprocessor must write a one to this bit to clear this interrupt. res - bits must always be written with zeros. diof - decompression input fifo overflow. this interrupt is generated when a write to an already full di fifo is performed. data written in this condition is lost. the only means of recovery from this error is to reset the fifo with the dirst bit. resetting the fifo causes this interrupt to clear. direqn is inactive while the interrupt is set. douf - decompression output fifo underflow. this interrupt is generated when a read from an empty do fifo is performed. once this interrupt is set, the do fifo must be reset with the dorst bit. the microprocessor must write a one to this bit to clear this interrupt. doreqn is inactive while the interrupt is set. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x06 res dorst dirst res address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x07 douf res diof res derr deor res
page 18 of 44 ps3422-0600 advanced hardware architectures, inc. 4.8 interrupt mask 0, address 0x09 - read/write this register is initialized to 0xff after reset. deorm - decompression end-of-record interrupt mask. when set to a one, prevents decompression end-of-record from causing intrn to go active. derrm - decompression error mask. when set to a one, prevents a decompression error (derr) from causing intrn to go active. res - bits must always be written with zeros. diofm - decompression input fifo overflow mask. when set to a one, prevents a decompression input fifo overflow (diof) from causing intrn to go active. doufm - decompression output fifo underflow mask. when set to a one, prevents a decompression output fifo underflow (douf) from causing intrn to go active. 4.9 version, address 0x0a - read only version[7:0] - contains version number of the die. 4.10 decompression record length, address 0x0c, 0x0d, 0x0e, 0x0f - read/write these registers are initialized to 0xff after reset. drlen[31:0]-decompression record length. contains the number of bytes in a decompressed record. these registers provide different functions depending on whether the decompressor is in pass- through or decompression mode. in decompression mode, the data itself contains eor information and drlen is only used for error checking. drlen is decremented each time a byte leaves the decompressor. in decompression mode, a derr interrupt is issued if an eor is not read out of the decompressor when the counter expires or if an eor occurs before the counter expires (i.e., when the record lengths do not match). if the derr interrupt is masked, use of the drlen register is optional in decompression mode. in pass-through mode, drlen determines the size of records read out of the decompressor. the counter is decremented for each byte read into the decompressor. in either mode, the counter reloads when it reaches zero or when drlen[31:24] is written. reading drlen returns the number of bytes left in the count. the lower three bytes of this register may be prearmed since the counter is automatically reloaded at the end of a record when the part is not programmed to pause on end-of-record. the upper byte is not prearmable since writing to this byte triggers an immediate reload to the counter. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x09 doufm res diofm res derrm deorm res address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0a version[7:0] address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0c drlen[7:0] 0x0d drlen[15:8] 0x0e drlen[23:16] 0x0f drlen[31:24]
ps3422-0600 page 19 of 44 advanced hardware architectures, inc. 4.11 decompression control, address 0x18 - read/write this register is initialized to 0x04 after reset. this register can be prearmed. dpor - decompression pause on record boundaries. when this bit is set to one, the decompressor stops taking data from the input fifo once a record boundary is found. upon finding the record boundary, dcomp is cleared. this bit may only be changed when dcomp is set to zero. after system reset or ddr, this bit is cleared. dcomp - decompression. setting this bit to a one enables the decompression engine (or pass-through mode if dpass is set) to take data from the decompression input fifo. if this bit is cleared, decompression stops. the bit is automatically cleared at the end of a record if dpor is set. decompression can be restarted without loss of data by setting dcomp. after system reset or ddr, this bit is cleared. demp - decompression engine empty. this bit is set when the decompression engine is cleared of data. writing to this bit has no effect. after system reset, this bit is set. ddr - decompression dictionary reset. setting this bit immediately resets the decompressor including the decompression dictionary. the reset condition remains active until the microprocessor writes a zero to this bit. dpass - decompression pass-through mode. while this bit is set, data is passed directly through the decompression engine without any effect on the data. this bit may only be changed when decompression is disabled (dcomp=0) and the decompression engine is empty of data (demp=1). the pass-through operation is started by setting dcomp. to stop the pass-through operation, dcomp should be cleared (to pause operation) and then dpass may be cleared. dpot - decompression pause on transfer boundaries. when this bit is set the decompressor stops taking data from the input fifo once a decompression end of transfer boundary is found indicated by the decompression record counter decrementing to zero. dblank - decompression blank record. the data in the next record output from the decompressor is a repeating byte pattern using the 8-bit data defined in the pattern register. dblank automatically clears at the end of the record when the decompression record count decrements to zero. when using dblank to generate a blank record the device must not contain data to be decompressed and the system must not send data to be decompressed for any future records until the part has reached the end-of-record for the blank record. also, the user must not set the dcomp bit when the dblank bit is set. dprearm -prearm enable. when this bit is set, decompression control prearm register is loaded into the decompression control register when the next end of record leaves the decompressor. 4.12 decompression reserved, address 0x1a, 0x3a - read/write this register is used for production testing only. initialized to 0x00 after reset. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x18 dprearm dblank dpot dpass ddr demp dcomp dpor address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x1a res 0x3a res
page 20 of 44 ps3422-0600 advanced hardware architectures, inc. 4.13 decompression line length, address 0x1c, 0x1d - read/write this register contains information necessary for the decompression operation. it must be set prior to any decompression operation. it should only be changed between records when dcomp is cleared and demp is set. these registers are undefined after reset. res - bits must always be written with zeros. line[10:0]-line length. the number of bytes in the scan line. minimum value is 16. for scan line lengths larger than the maximum allowed, set to 16. 4.14 interrupt status/control 1, address 0x27 - read/write this register is initialized to 0x00 after reset. deot - decompression end-of-transfer interrupt. this bit is set when a decompression end of transfer condition is reached indicated by the decompression record counter counting down to zero. the microprocessor must write a one to this bit to clear this interrupt. res - bits must always be written with zeros. 4.15 interrupt mask 1, address 0x29 - read/write this register is initialized to 0xff after reset. deotm - decompression end-of-transfer interrupt mask. when set to a one, prevents decompression end-of-transfer from causing intrn to go active. res - bits must always be written with zeros. res - bits must always be written with zeros. 4.16 decompression record count, address 0x2c, 0x2d - read/write these registers are initialized to 0xffff after reset. drc[15:0] -decompression record count is the number of records in the current transfer. the internal record counter latches the value in this register when drc[15:8] is written. the internal counter is decremented as the last byte of the record is decompressed. at the end-of-transfer, the value in this register is reloaded into the internal record counter. reading this register address returns the internal record counter value. expiration of this counter causes the deot interrupt to be posted. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x1c line[7:0] 0x1d res line[10:8] address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x27 res deot res address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x29 res deotm res address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x2c drc[7:0] 0x2d drc[15:8]
ps3422-0600 page 21 of 44 advanced hardware architectures, inc. 4.17 pattern, address 0x35 - read/write this register is undefined after reset. pattern[7:0]-pattern is the 8-bit data used to generate blank bands or records. if dblank is set, the part outputs this register value repeatedly for the entire record (or band). 4.18 decompression control prearm, address 0x38 - read/write this register initializes to 0x00 after reset. this register is cleared when the prearm loads into the decompression control register, thus providing a method for the user to verify that the prearm loaded. note, the user must not change modes of operation between decompression, pass-through and blank when there is data in the decompressor. see decompression control register for bit descriptions. this register is the prearm register for the decompression control register. res - bits must always be written with zeros. 4.19 control, address 0x3f - read/write this register must be written with 0x0e before a decompression or pass-through operation begins. default after reset is 0x0f. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x35 pattern[7:0] address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x38 ndprearm ndblank ndpot ndpass nddr res ndcomp ndpor address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x3f control code
page 22 of 44 ps3422-0600 advanced hardware architectures, inc. 5.0 signal descriptions this section contains descriptions for all the pins. each signal has a type code associated with it. the type codes are described in the following table. 5.1 microprocessor interface type code description i input only pin o output only pin i/o input/output pin s synchronous signal a asynchronous signal microprocessor interface signal type description pd[7:0] i/o s processor data. data for all microprocessor reads and writes of registers within aha3422 are performed on this bus. this bus may be tied to the data bus, d[31:0], provided microprocessor accesses do not occur at the same time as dma accesses. pa[5:0] i s processor address bus. used to address internal registers within aha3422. csn i s chip select. selects aha3422 as the source or destination of the current microprocessor bus cycle. csn needs only be active for one clock cycle to start a microprocessor access. dir i s direction. this signal indicates whether the access to the register specified by the pa bus is a read or a write. the polarity of this signal is programmed with the procmode0 pin. rdyn o a,s ready. indicates valid data is on the data bus during read operation and completion of write operation. its operation depends on procmode[1:0] settings. intrn o s interrupt. the compression and decompression processes generate interrupts that are reported with this signal. intrn is low whenever any non-masked bits are set in the interrupt status/control register. procmode[1:0] i s microprocessor port configuration mode. selects the polarity of the dir pin and operation of the csn pin. refer to section 2.1 microprocessor interface for details. (figure 2 through figure 5)
ps3422-0600 page 23 of 44 advanced hardware architectures, inc. 5.2 data interface 5.3 video interface data interface signal type description d[31:0] i/o s data for all channels is transmitted on this bus. the ackn is used to distinguish between the four channels. data being written to aha3422 is latched on the rising edge of clock when the strobe condition is met. data setup and hold times are relative to clock. if the bus is configured to 16-bit transfers (wide=0), data is carried on d[15:0]. in this case, d[31:16] should be terminated with pullup resistors. driven i a drive enable. active low output driver enable. this input must be low in order to drive data onto d[31:0] in accordance with the current strobe condition. sd i s strobe delay. active high. allows insertion of wait states for dma access to the fifos. the strobe condition, as programmed in the dsc field of system configuration 1 , enables this signal and selects its polarity. direqn o s decompression input data request, active low. when this signal is active, it indicates the ability of the di port to accept data. diackn i s decompression input data acknowledge. active low decompression data input. when this signal is active, it indicates the data on d is for the decompression input port. data on d is latched on the rising edge of clock when the strobe condition is met. doreqn o a, s decompression output data request, active low. when this signal is active, it indicates the ability of the do port to transmit data. doackn i s decompression output data acknowledge. the definition of doackn varies with the data strobe condition in system configuration 1 . see table 4. video interface signal type description voreqn o s video output request. active low output indicating that the byte on vod[7:0] is valid. voackn i s video output acknowledge. active low input indicating that the external system is ready to read vod[7:0]. vod[7:0] o s video output data. the value on this output bus is read when both voreqn and voackn are low. voeorn o s video output end of record is active low indicating the byte on vod[7:0] contains the last byte in a record. voeotn o s video output end of transfer is active low indicating the byte on vod[7:0] contains the last byte in a multi-record transfer.
page 24 of 44 ps3422-0600 advanced hardware architectures, inc. 5.4 system control system control signal type description clock i system clock. this signal is connected to the clock of the microprocessor. the intel i960cx calls this pin pclk. rstn i a power on reset. active low reset signal. the device must be reset before any dma or microprocessor activity is attempted. rstn should be a minimum of 10 clock periods. test0 i a board test mode. when test is high, all outputs are tristated. when test is low, the chip performs normally. test1 i a used for production tests. this input should always be tied low.
ps3422-0600 page 25 of 44 advanced hardware architectures, inc. 6.0 pinout *note: the pins marked vdd or vss can be connected to either vdd or vss but should not be left unconnected. pin signal pin signal pin signal 1 vdd or vss* 44 vss 87 vod[7] 2 vdd or vss* 45 vss 88 nc 3 vdd or vss* 46 vdd 89 vdd 4 vdd or vss* 47 clock 90 vss 5 vdd or vss* 48 vss 91 voackn 6 intrn 49 vdd 92 test0 7 vss 50 vdd 93 pa[0] 8 vdd 51 vss 94 pa[1] 9 driven 52 vdd 95 pa[2] 10 sd 53 d[15] 96 pa[3] 11 doackn 54 d[16] 97 vdd 12 vdd 55 d[17] 98 pa[5] 13 diackn 56 d[18] 99 vss 14 vdd 57 d[19] 100 pa[4] 15 vss 58 d[20] 101 nc 16 vdd 59 d[21] 102 voeotn 17 doreqn 60 d[22] 103 procmode[1] 18 nc 61 d[23] 104 procmode[0] 19 direqn 62 d[24] 105 csn 20 nc 63 vss 106 vdd 21 nc 64 vdd 107 vss 22 d[0] 65 d[25] 108 dir 23 vss 66 d[26] 109 rstn 24 vss 67 d[27] 110 pd[7] 25 vdd 68 d[28] 111 pd[6] 26 vdd 69 d[29] 112 pd[5] 27 d[1] 70 d[30] 113 vdd 28 d[2] 71 vdd 114 vss 29 d[3] 72 vdd 115 pd[4] 30 d[4] 73 vss 116 pd[3] 31 d[5] 74 vss 117 pd[2] 32 d[6] 75 d[31] 118 pd[1] 33 d[7] 76 voreqn 119 pd[0] 34 d[8] 77 voeorn 120 vdd 35 d[9] 78 vod[0] 121 vss 36 d[10] 79 vod[1] 122 rdyn 37 d[11] 80 vod[2] 123 vdd 38 vss 81 vdd 124 vdd or vss* 39 vdd 82 vss 125 vdd or vss* 40 d[12] 83 vod[3] 126 vdd or vss* 41 d[13] 84 vod[4] 127 vdd 42 d[14] 85 vod[5] 128 vss 43 test1 86 vod[6]
page 26 of 44 ps3422-0600 advanced hardware architectures, inc. figure 15: pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 33 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 pa[3] pa[2] pa[1] pa[0] test0 voackn vss vdd nc vod[7] vod[6] vod[5] vod[4] vod[3] vss vdd vod[2] vod[1] vod[0] voeorn voreqn d[31] vss vss vdd vdd d[30] d[29] d[28] d[27] d[26] d[25] vdd vss d[24] d[23] d[22] d[21] d[20] d[19] d[18] d[17] d[16] d[15] vdd vss vdd vdd vss clock vdd vss vss test1 d[14] d[13] d[12] vdd vss d[11] d[10] d[9] d[8] d[7] *i *i *i *i *i intrn vss vdd driven sd doackn vdd diackn vdd vss vdd doreqn nc direqn nc nc d[0] vss vss vdd vdd d[1] d[2] d[3] d[4] d[5] d[6] vdd pa[5] vss pa[4] nc voeotn procmode[1] procmode[0] csn vdd vss dir rstn pd[7] pd[6] pd[5] vdd vss pd[4] pd[3] pd[2] pd[1] pd[0] vdd vss rdyn vdd *i *i *i vdd vss nc = no connect aha3422a-033 pqc *i = connect to vdd or vss
ps3422-0600 page 27 of 44 advanced hardware architectures, inc. 7.0 dc electrical specifications 7.1 operating conditions notes: 1) dynamic current; no data transfers 2) static current (clock high) 3) timings referenced to this load 4) iload = 0 ma 7.2 absolute maximum stress ratings operating conditions symbol parameter min max units notes vdd supply voltage 4.75 5.25 v idd supply current (active) 300 ma 4 idd supply current (standby) 80 ma 1, 4 idd supply current (low power) 1 ma 2, 4 ta ambient temperature 0 70 c vil input low voltage: procmode[1:0], test0, test1 other signals vss-0.5 vss-0.5 0.3 vdd 0.8 v vih input high voltage: procmode[1:0], test0, test1 other signals 0.7 vdd 2.0 vdd+0.5 vdd+0.5 v iil input leakage current -10 10 a vol output low voltage (iol=-4ma) 0.4 v voh output high voltage (ioh=4ma) 2.4 v voh output high voltage (ioh=100 a) vdd-0.8 v iol output low current 4 ma ioh output high current -4 ma ioz output leakage current -10 10 a ioz high impedance leakage current -10 10 a cin input capacitance 5 pf cout output capacitance 7 pf cio input/output capacitance 7 pf comax maximum capacitance load for all signals (including self loading) 50 pf 3 absolute maximum stress ratings symbol parameter min max units notes tstg storage temperature -50 150 c vdd supply voltage -0.5 7 v vin input voltage vss-0.5 vdd+0.5 v
page 28 of 44 ps3422-0600 advanced hardware architectures, inc. 8.0 ac electrical specifications notes: 1) production test condition is 50 pf. output delay is decreased 2 ns with 25 pf load guaranteed by design or characterization. 2) all timings are referenced to 1.4 volts. figure 16: data interface timing table 6: data port timing requirements figure 17: request deasserts at eor, strobe condition of dsc=0-3, 6-15; erc=0 number parameter min max units 1 diackn, doackn and sd setup time 8 ns 2 diackn, doackn and sd hold time 2 ns 3 d-bus input setup time 8 ns 4 d-bus input hold time 2 ns 5 reqn delay (non-eor case) 18 ns 6 reqn hold (non-eor case) 2 ns clock d reqn d/ coeorn ackn/ sd valid 0 valid valid 1 1 2 3 4 6 5 7 8 clock ackn reqn d sd eor-1 eor 1 2
ps3422-0600 page 29 of 44 advanced hardware architectures, inc. figure 18: request deasserts at eor, strobe condition of dsc=0-3, 6-15; erc=1 figure 19: request deasserts at eor, strobe condition of dsc=4 or 5; erc=0 figure 20: request deasserts at eor, strobe condition of dsc=4 or 5; erc=1 table 7: request vs. eor timing number parameter min max units 1 ackn, sd to reqn erc=0 16 ns 2 clock to reqn erc=0 16 ns 3 clock to reqn dsc=0-3, 6, 7; erc=1 16 ns 4 clock to reqn dsc=4, 5; erc=0 16 ns 5 clock to reqn dsc=4, 5; erc=1 16 ns clock ackn reqn d sd eor-1 eor 3 clock ackn reqn d sd eor-1 eor 4 clock ackn reqn d sd eor-1 eor 5
page 30 of 44 ps3422-0600 advanced hardware architectures, inc. figure 21: output enable timing table 8: output enable timing requirements figure 22: video output port timing table 9: video output port timing requirements number parameter min max units 1 driven to d valid 15 ns 2 driven to d tristate 10 ns 3 signal to d valid 15 ns 4 signal to d tristate 10 ns 5 clock to d tristate (dsc=100, 101) 15 ns number parameter min max units 1 voreqn delay 16 ns 2 voreqn hold 2 ns 3 voackn setup 8 ns 4 voackn hold 2 ns 5 vod delay 16 ns 6 vod hold 2 ns 7 voeorn hold 2 ns 8 voeorn delay 16 ns clock ackn driven d 2 1 3 4 5 clock voackn vod[7:0] voreqn 1 2 4 3 6 voeorn 5 7 8
ps3422-0600 page 31 of 44 advanced hardware architectures, inc. figure 23: microprocessor interface timing (procmode[1]=0) figure 24: microprocessor interface timing (procmode[1]=1) clock csn pa rdyn dir read 1 1 21 2 3 4 6 9 10 910 15 14 3 4 7 8 9 10 12 13 valid tristate valid tristate 910 valid pd dir pd write 234512 clock csn pa rdyn dir read 1 pd dir pd write 123 5n 4 valid valid a0 3 2 4 16 17 12 7 14 15 9 13 tristate 10
page 32 of 44 ps3422-0600 advanced hardware architectures, inc. table 10: microprocessor interface timing requirements figure 25: interrupt timing table 11: interrupt timing requirements figure 26: clock timing table 12: clock timing requirements number parameter min max units 1 pa setup time 8 ns 2 pa hold time 2 ns 3 csn setup time 8 ns 4 csn hold time 2 ns 6 csn to valid rdyn 15 ns 7 rdyn valid delay 16 ns 8 rdyn drive disable 10 ns 9 dir setup time 8 ns 10 dir hold time 2 ns 12 pd valid delay 16 ns 13 pd drive disable 12 ns 14 pd setup time 8 ns 15 pd hold time 2 ns 16 csn high to pd tristate 10 ns 17 csn high to rdyn high 15 ns number parameter min max units 1 intrn delay time 15 ns 2 intrn hold time 2 ns number parameter min max units 1 clock rise time 2 ns 2 clock fall time 2 ns 3 clock high time 12 ns 4 clock low time 12 ns 5 clock period 30 ns clock intrn 1 2 clk 1 34 5 2 2.0v 1.4v 0.8v
ps3422-0600 page 33 of 44 advanced hardware architectures, inc. figure 27: power on reset timing table 13: power on reset timing requirements notes: 1) rstn signal can be asynchronous to the clock signal. it is internally synchronized to the rising edge of clock. number parameter min max units 1 rstn low pulsewidth 10 clocks 2 rstn setup to clock rise 15 ns 3 rstn hold time 2 ns clock rstn 2 3 1
page 34 of 44 ps3422-0600 advanced hardware architectures, inc. 9.0 package specifications jedec outline is mo-108 l a a detail a a2 a1 e1 d1 p p d b e 125 126 127 128 32 31 30 29 28 aha3422a-033 pqc 97 98 99 100 (lca) (lcb)
ps3422-0600 page 35 of 44 advanced hardware architectures, inc. 10.0 ordering information 10.1 available parts 10.2 part numbering device number: 3422 revision letter: a package material codes: p plastic package type codes: q quad flat pack test specifications: c commercial 0 c to +70 c plastic quad flat pack package dimensions symbol number of pin and specification dimension 128 sb min nom max (lca) 32 (lcb) 32 a 3.7 4.07 a1 0.25 0.33 a2 3.2 3.37 3.6 d 30.95 31.2 31.45 d1 27.99 28 28.12 e 30.95 31.2 31.45 e1 27.99 28 28.12 l 0.73 0.88 1.03 p0.8 b 0.3 0.35 0.4 part number description aha3422a-033 pqc 16 mbytes/sec lossless decompressor ic aha 3422 a- 033 p q c manufacturer device number revision level speed designation package material package type test specification
page 36 of 44 ps3422-0600 advanced hardware architectures, inc. 11.0 related technical publications document # description ps3410c aha product specification ? aha3410c starlite tm 25 mbytes/sec simultaneous lossless data compression/decompression coprocessor ic ps3411 aha product specification ? aha3411 starlite tm 33 mbytes/sec simultaneous compressor/decompressor ic ps3431 aha product specification ? aha3431 starlite tm 40 mbytes/sec simultaneous compressor/decompressor ic, 3.3v pb3410c aha product brief ? aha3410c starlite tm 25 mbytes/sec simultaneous lossless data compression/decompression coprocessor ic pb3411 aha product brief ? aha3411 starlite tm 33 mbytes/sec simultaneous compressor/ decompressor ic pb3422 aha product brief ? aha3422 starlite tm 16 mbytes/sec lossless decompressor ic pb3431 aha product brief ? aha3431 starlite tm 40 mbytes/sec simultaneous compressor/ decompressor ic, 3.3v abdc18 aha application brief ? aha3410c, aha3411 and aha3431 device differences andc12 aha application note ? aha3410c starlite tm designer ? s guide andc13 aha application note ? compression performance on bitonal images andc14 aha application note ? starlite tm evaluation software andc15 aha application note ? encodeb2 compression algorithm description andc16 aha application note ? designer ? s guide for starlite tm family products: aha3411, aha3422 and aha3431 andc17 aha application note ? starlite tm compression on continuous tone images glgen1 general glossary of terms starsw starlite tm evaluation software (windows tm )
ps3422-0600 page 37 of 44 advanced hardware architectures, inc. appendix a: additional timing diagrams for dma mode transfers figure a1: dma mode timing for single word writes, strobe condition of dsc=000 figure a2: dma mode timing for single word reads, strobe condition of dsc=000 figure a3: dma mode timing for four word burst write, one wait state, strobe condition of dsc=000 clock ackn sd driven d d0 d1 clock ackn sd driven d d1 d0 clock ackn sd driven d d0 d2 d1 d3
page 38 of 44 ps3422-0600 advanced hardware architectures, inc. figure a4: dma mode timing for four word burst read, one wait state, strobe condition of dsc=000 figure a5: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=000 figure a6: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=000 clock ackn sd driven d d1 d0 d2 d3 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7
ps3422-0600 page 39 of 44 advanced hardware architectures, inc. figure a7: dma mode timing for single word writes, strobe condition of dsc=010 figure a8: dma mode timing for single word reads, strobe condition of dsc=010 figure a9: dma mode timing for four word burst write, one wait state, strobe condition of dsc=010 clock ackn sd driven d d0 d1 clock ackn sd driven d d1 d0 clock ackn sd driven d d0 d2 d1 d3
page 40 of 44 ps3422-0600 advanced hardware architectures, inc. figure a10: dma mode timing for four word burst read, one wait state, strobe condition of dsc=010 figure a11: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=010 figure a12: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=010 clock ackn sd driven d d1 d0 d2 d3 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7 clock ackn sd driven d d2 d1 d3 d4 d5 d6 d7 d0
ps3422-0600 page 41 of 44 advanced hardware architectures, inc. figure a13: dma mode timing for single word writes, strobe condition of dsc=011 figure a14: dma mode timing for single word reads, strobe condition of dsc=011 figure a15: dma mode timing for four word burst write, one wait state, strobe condition of dsc=011 clock ackn sd driven d d0 d1 clock ackn sd driven d d1 d0 clock ackn sd driven d d0 d2 d1 d3
page 42 of 44 ps3422-0600 advanced hardware architectures, inc. figure a16: dma mode timing for four word burst read, one wait state, strobe condition of dsc=011 figure a17: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=011 figure a18: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=011 clock ackn sd driven d d1 d0 d2 d3 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7 clock ackn sd driven d d2 d1 d3 d4 d5 d6 d7 d0
ps3422-0600 page 43 of 44 advanced hardware architectures, inc. figure a19: dma mode timing for single word writes, strobe condition of dsc=111 figure a20: dma mode timing for single word reads, strobe condition of dsc=111 clock ackn sd driven d d0 d1 d2 clock ackn sd driven d d1 d0 d2
page 44 of 44 ps3422-0600 advanced hardware architectures, inc. appendix b: sequential register table address description 00 system configuration 0 01 system configuration 1 02 input fifo thresholds 03 output fifo thresholds 04 reserved 05 decompression ports status 06 port control 07 interrupt status/control 0 09 interrupt mask 0 0a version 0c decompression record length 0 0d decompression record length 1 0e decompression record length 2 0f decompression record length 3 10 reserved 11 reserved 12 reserved 13 reserved 14 reserved 15 reserved 16 reserved 17 reserved 18 decompression control 1a decompression reserved 1 1c decompression line length 0 1d decompression line length 1 20 reserved 21 reserved 27 interrupt status/control 1 29 interrupt mask 1 2c decompression record count 0 2d decompression record count 1 30 reserved 31 reserved 32 reserved 33 reserved 34 reserved 35 pattern 38 decompression control prearm 3f control

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